CREC (2003)

July 5, 2026

In the early 2000s, a small research group in the Computer Science Department of the Technical University of Cluj-Napoca set out to answer an unusual question: instead of writing software to fit a fixed processor, what if you generated the processor to fit the software? The result was CREC, a low-cost, general-purpose reconfigurable computer whose hardware architecture was synthesised, application by application, through a hardware/software co-design process. The project’s name traces back to its lead researcher, Octavian Creţ.

This is a retrospective on what CREC was, how it worked, and where my own contributions to it sit.

The core idea#

Conventional computing fixes the hardware and varies the software. Reconfigurable computing, which is built on FPGAs whose logic can be rewired after manufacture, lets you move the boundary. Most reconfigurable-computing research of the era chased a narrow target: fine-grained, massively parallel, low-level operations like image filters or bit manipulation.

CREC was more ambitious. It aimed to be general-purpose: take an ordinary program, analyse it, and emit a bespoke hardware architecture that best suited that specific program. The premise was that many computations carry a lot of intrinsic parallelism that a sequential CPU simply throws away. If you could extract that parallelism and bake it directly into silicon-like logic, you would win it back at run time.

How it worked#

The pipeline had a distinctive shape:

1. A parallel compiler parsed the source program and analysed its structure, extracting parallelism and mapping the work onto multiple Execution Units, the building blocks of the generated machine.
2. The compiler then produced a description of the resulting hardware architecture in VHDL, the hardware description language. Crucially, this VHDL wasn’t hand-written. It was generated by a program, so the whole flow was automatic.
3. That VHDL was synthesised and implemented on an FPGA device (the prototype work targeted a Virtex-E family part), turning the program-specific architecture into running hardware.

A few design decisions gave CREC its character:

• Deliberately low-cost and portable. CREC relied only on classical, off-the-shelf FPGA devices, standard VHDL, and a mainstream high-level language, with no dependence on a custom VLSI chip. That set it apart from richer but far more expensive academic systems of the day such as MorphoSys, Garp, or Chimera.
• A compact RISC-style instruction model. CREC defined its own assembly language in a RISC spirit, with every instruction encoded on the same number of bits, a clean, regular target for the compiler to emit.
• Multiple configuration contexts per element. Rather than holding a single configuration, each reconfigurable computing element could locally store several configuration contexts. This was treated as one of the system’s defining features, letting the machine switch behaviour quickly without a full external reconfiguration.
• A conscious compile-time / run-time trade-off. Generating and synthesising custom hardware is slow. The team’s argument was that for workloads with long execution times (image processing, pattern recognition, genetic algorithms, sequence alignment) the up-front compilation cost is repaid many times over by parallel execution replacing the classical sequential path.

From concept to methodology#

CREC evolved across a cluster of papers. The earliest work, The CREC Reconfigurable Computer: Preliminary Findings (Timişoara, 2002) and CREC: A Novel Reconfigurable Computing Design Methodology (IPDPS 2003, Nice), laid out the concept, the design flow, and the development system, and were authored by Creţ, Pusztai, Vancea, and Szente.

Through 2003 the project matured from a proof-of-concept into a more fully specified methodology and system, and that is the phase I was part of.

Where I contributed#

My name appears as a co-author on the three 2003 papers that carried CREC from initial concept into a documented general-purpose methodology and system description:

• “A hardware/software codesign method for general purpose reconfigurable computing”, in the Proceedings of the 14th International Conference on Control Systems and Computer Science (CSCS-14), Bucharest, July 2003. Co-authors: Octavian Creţ, Kalman Pusztai, Cristian Vancea, Balint Szente, Ligiu Uiorean, Adrian Dărăbant. This paper set out the co-design method itself, the process by which a program becomes application-specific hardware.
• “The CREC general purpose reconfigurable computer”, at the IP Based Design Workshop, Grenoble, November 2003. Co-authors: Balint Szente, Cristian Vancea, Ligiu Uiorean, Florin Rusu, Octavian Creţ, Kalman Pusztai.
• “The CREC Reconfigurable Computer”, in the Proceedings of the 1st Balkan Conference in Informatics (BCI), Thessaloniki, November 2003. Co-authors: Octavian Creţ, Cristian Vancea, Balint Szente, Ligiu Uiorean, Florin Rusu.

In other words, my involvement is concentrated in the 2003 body of work, the year CREC was written up as a complete general-purpose system and co-design methodology, and presented internationally (Bucharest, Grenoble, and Thessaloniki) rather than only in the initial concept papers.

After 2003#

Once I moved on, CREC stopped being described as a concept and started being used. The arc runs from roughly 2004 to 2006:

• 2004-2005: a real bioinformatics workload. The group’s main effort was implementing the general Smith-Waterman sequence-alignment algorithm on CREC. Where earlier hardware attempts only handled special cases, the CREC version tackled the general case and reached efficiency close to dedicated systolic designs, with a large speedup over a PC. It was presented at the IASTED PDCS 2004 symposium at MIT, then published as a journal paper in 2005.
• 2005: consolidation and a turn to dynamic reconfiguration. A comparative study benchmarked three Smith-Waterman implementations against each other (CSCS-15, Bucharest), and a sibling paper explored run-time reconfiguration using JBits and modular design, a different technique from CREC’s compile-time hardware generation. Octavian Creţ also gathered the accumulated work into a Romanian monograph, Sisteme de calcul reconfigurabile (UTPres, 2005).
• 2006: the pivot to “hardware agents.” The explicit CREC name largely fades. The group reframed the same idea, FPGA hardware synthesised from a high-level problem, as hardware-agents-based systems, applied to the maximum-subsequence problem (Kadane’s algorithm) at ICCP 2006 and in WSEAS venues.

The team composition drifted over these years too: Zsolt and Ştefan Mathe, Lucia Văcariu and Adrian Dărăbant became central, while the 2003 cohort stayed involved through the Smith-Waterman phase and then tapered off.

Legacy#

After 2003 the CREC platform became a substrate for other people’s algorithms. The group used it to build a scalable, FPGA-based implementation of the general Smith-Waterman sequence-alignment algorithm (presented at MIT in 2004 and in follow-on comparative studies), and later work applied hardware-agent approaches to problems like Kadane’s maximum-subsequence algorithm. That afterlife is arguably the best evidence that the original goal held up: a general-purpose reconfigurable machine that real, demanding applications could actually be built on.

Two decades on, the central CREC bet, compile the hardware to the program rather than the program to the hardware, reads less like a curiosity and more like an early sighting of ideas now mainstream in domain-specific accelerators, high-level synthesis, and compiler-architecture co-design.

Where the team is now#

• Octavian Creţ, the project lead, now a full Professor of computer science in Cluj (recently listed at Babeş-Bolyai University), who stayed in the FPGA field with later work on partial reconfiguration, true-random-number generators, and malware detection.
• Kalman Pusztai, the senior professor and Creţ’s PhD supervisor, a pioneer of Romania’s early internet who is honoured by the “Kalman Pusztai” data-communications centre that still bears his name at the Technical University of Cluj-Napoca.
• Cristian Cosmin Vancea, who stayed at the Technical University of Cluj-Napoca, earning his PhD there in 2020 and becoming a Senior Lecturer working in image processing and computer vision for automated driving.
• Florin Rusu, who moved to the US after his 2004 Cluj degree and is now a Professor of Computer Science and Engineering at UC Merced, specialising in databases and large-scale data management.
• Adrian Sergiu Dărăbant, now a Professor in the Computer Science department of Babeş-Bolyai University, working on image processing, deep learning, and databases.
• Balint Szente, associated at the time of CREC with “Petru Maior” University of Târgu-Mureş, and now an engineering manager at Bitdefender.

References#

• O. Creţ, K. Pusztai, C. Vancea, B. Szente. The CREC Reconfigurable Computer: Preliminary Findings. Transactions on Automatic Control and Computer Science, tome 47(61), no. 2, pp. 77-82, Periodica Politehnica, TU Timişoara, October 2002. ISSN 1224-600X.
• O. Creţ, K. Pusztai, C. Vancea, B. Szente. CREC: A Novel Reconfigurable Computing Design Methodology. Proc. 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), Nice, France, April 2003, p. 175.
• O. Creţ, K. Pusztai, C. Vancea, B. Szente, L. Uiorean, A. Dărăbant. A hardware/software codesign method for general purpose reconfigurable computing. Proc. 14th International Conference on Control Systems and Computer Science, Bucharest, July 2003, pp. 57-63. ISBN 973-8449-18-9.
• B. Szente, C. Vancea, L. Uiorean, F. Rusu, O. Creţ, K. Pusztai. The CREC general purpose reconfigurable computer. Proc. IP Based Design Workshop, Grenoble, France, November 2003, p. 217.
• O. Creţ, C. Vancea, B. Szente, L. Uiorean, F. Rusu. The CREC Reconfigurable Computer. Proc. 1st Balkan Conference in Informatics, Thessaloniki, Greece, November 2003, p. 476. ISBN 960-287-045-1.
• B. Szente, O. Creţ, Z. Mathe, C. Vancea, F. Rusu. A General Smith-Waterman Algorithm Implementation Using the CREC Reconfigurable Computer. ACAM Scientific Journal, vol. 14(2), pp. 227-232, Mediamira, Cluj-Napoca, 2005. ISSN 1221-437X.